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[Other resource] 基于CPLD-FPGA的半整数分频器的设计

Description: 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
Platform: | Size: 21359 | Author: 胡路听 | Hits:

[Other resource] FPGAprogram2

Description: 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
Platform: | Size: 3379 | Author: 许嘉 | Hits:

[VHDL-FPGA-Verilog] 基于CPLD-FPGA的半整数分频器的设计

Description: 基于CPLD-FPGA的半整数分频器的设计，用于设计EDA-based CPLD-half FPGA integer dividers in the design, design for EDA
Platform: | Size: 21504 | Author: 胡路听 | Hits:

[VHDL-FPGA-Verilog] FPGAprogram2

Description: 半整数分频器电路的VHDL源程序，供大家学习和讨论。 -half-integer frequency divider circuit VHDL source code for all learning and discussion.
Platform: | Size: 3072 | Author: 许嘉 | Hits:

[VHDL-FPGA-Verilog] Verilog_FPGA_fp

Description: 用Verilog实现基于FPGA的通用分频器-using Verilog FPGA-based Universal Frequency Divider
Platform: | Size: 124928 | Author: xiong | Hits:

[SCM] 9

Description: 本文介绍了两种分频系数为整数或半整数的可控分频器的设计方法。其中之一可以实现50％的奇数分频。利用VHDL语言编程，并用QUARTERS||4.0进行仿真，用 FPGA 芯片实现。 关键词：半整数，可控分频器，VHDL, FPGA -This article describes two kinds of sub-frequency coefficient is an integer or half-integer divider controllable design method. One of them can achieve 50 of the odd-numbered sub-frequency. The use of VHDL language programming, and QUARTERS | | 4.0 simulation, using FPGA chip. Key words: semi-integer, controllable divider, VHDL, FPGA
Platform: | Size: 180224 | Author: 陈金豹 | Hits:

[VHDL-FPGA-Verilog] 2008082018202568

Description: 0到255任意整数半整数分频Verilog HDL.rar-0-255 arbitrary integer half-integer frequency division Verilog HDL.rar
Platform: | Size: 3072 | Author: zw | Hits:

[Software Engineering] 15

Description: 半整数分频器的设计 请不要上传有版权争议的内容和木马病毒代码 -Half-integer divider design, please do not upload copyrighted content and controversial Trojan code
Platform: | Size: 71680 | Author: 顾春辉 | Hits:

[VHDL-FPGA-Verilog] Half

Description: 半整数分频，可以分出x.5的频率，大家请自行研究其他频率。-Half-integer frequency, the frequency may be distinguished x.5, we requested to look into other frequencies.
Platform: | Size: 1024 | Author: 江山 | Hits:

[Multimedia program] EBMA

Description: Integer-pel EBMA and Half-pel EBMA
Platform: | Size: 2048 | Author: 张华君 | Hits:

[VHDL-FPGA-Verilog] VHDL_fre_div

Description: 使用VHDL进行分频器设计 本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设 计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数 （N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可 通过Synplify Pro或FPGA生产厂商的综合器进行综合，形成可使 用的电路，并在ModelSim上进行验证。-For crossover design using VHDL This paper describes the use of examples in the FPGA/CPLD design using VHDL for divider Design, including even frequency, duty cycle and 50 of non-50 duty cycle of the odd frequency, half-integer (N+0.5) frequency, fractional, fractional and integral crossover frequency. Can all achieve Synplify Pro FPGA by or integrated device manufacturers an integrated, enables the formation of With the circuit, and on the ModelSim verification.
Platform: | Size: 322560 | Author: guoguo | Hits:

[VHDL-FPGA-Verilog] fenpin

Description: 分频电路的研究 主要包括：偶数分频（二分频、偶数分频占空比50 ）、奇数分频（占空比50 、占空比非50 ）、半整数分频（不要求占空比）、小数分频（不要求占空比）。 -Frequency of the circuit includes: an even frequency (half frequency, frequency 50 duty cycle even), odd-frequency (50 duty cycle, duty cycle of non-50 ), half-integer frequency division (not required duty cycle), fractional (not required duty cycle).
Platform: | Size: 16384 | Author: lishaohui | Hits:

[Other systems] Motion_compensation_N_estimation

Description: Motion compensation and estimation. EBMA integer pel and EBMA half pel used to estimate the image. Foreman66 and Foreman72 are enclosed t-Motion compensation and estimation. EBMA integer pel and EBMA half pel used to estimate the image. Foreman66 and Foreman72 are enclosed too
Platform: | Size: 152576 | Author: melissanais | Hits:

[VHDL-FPGA-Verilog] VHDLdesignexamples

Description: 半整数分频器、音乐发生器、信号产生器、多功能电子表、交通控制灯、数字频率计的设计实例及习题-Half-integer divider, music generator, signal generator, multi-function digital watch, traffic control lights, digital frequency meter design examples and exercises
Platform: | Size: 456704 | Author: 张怀卿 | Hits:

[VHDL-FPGA-Verilog] VHDL-divider-design

Description: VHDL分频器设计，本文使用实例描述了在FPGA/CPLD上使用VHDL进行分频器设计，包括偶数分频、非50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。-VHDL divider design, this article describes use cases, including even divide, non-50 duty cycle and 50 duty cycle odd divider, half integer (N+0-crossover design using VHDL for FPGA/CPLD .5) divider, fractional, fractional divider and integral divider.
Platform: | Size: 320512 | Author: 黄玲 | Hits:

[Special Effects] HBMA

Description: 基于整像素和半像素的HBMA算法实现，用于估计两帧图像间的误差并进行压缩-Based on half-integer pixel and pixel HBMA algorithm for error estimation between two images and compressed
Platform: | Size: 2048 | Author: | Hits:

[VHDL-FPGA-Verilog] Half_Frequence

Description: 本程序基于VHDL语言，设计分频器，其中包含半整数分频占空比不为50 奇数分频占空比为50 任意小数分频 -The program is based on VHDL language design divider, which includes half-integer divider 50 duty cycle is not odd frequency 50 duty cycle any fractional
Platform: | Size: 24576 | Author: qikaiyi | Hits:

[VHDL-FPGA-Verilog] Prescaler-to-use-VHDL-design

Description: 本文使用实例描述了在 FPGA/CPLD 上使用 VHDL 进行分频器设计，包括偶数分频、非 50 占空比和50 占空比的奇数分频、半整数（N+0.5）分频、小数分频、分数分频以及积分分频。所有实现均可通过 Synplify Pro 或 FPGA 生产厂商的综合器进行综合，形成可使用的电路，并在 ModelSim 上进行验证。-This paper describes the use of examples prescaler to use VHDL design on FPGA/CPLD, including even frequency, non-50 duty cycle and 50 duty cycle odd frequency, half-integer (N+0.5) Divide, fractional, fractional and integral crossover frequency. All can be achieved through Synplify Pro FPGA synthesizer manufacturer or integrated to form a circuit that can be used and verified in ModelSim.
Platform: | Size: 339968 | Author: liufei | Hits:

[SCM] sadas

Description: 2D FDTD – UPML code with TF / SF formulation Notes :: E at half integer time intervals -2D FDTD – UPML code with TF/SF formulation Notes :: E at half integer time intervals and H at integer time integer time integer time integer time
Platform: | Size: 2048 | Author: 李墨伊 | Hits:

[VHDL-FPGA-Verilog] half_integer

Description: 数控分频器：以2.5分频为例的半整数分频器-half-integer frequency divider
Platform: | Size: 212992 | Author: litong | Hits:
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